Hardware Design & Lab Platform

Design smarter.
Validate faster.
Demo sooner.

Three products built on one platform. LabForge Design AI catches design flaws before silicon. LabForge Studio gives engineering teams an on-premises lab bench. Showcase turns your chip into a live customer demo.

LabForge Studio

Your lab bench.
On your network.
For every engineer.

Flash bitstreams, probe GPIO, step through JTAG breakpoints, and run regression suites against real hardware — without touching a physical lab. Deploy on your own infrastructure. Your IP never leaves your building.

labforge studio — alice · fpga-01 · session #a7f2
$lf lab create --board xilinx-au200
✓ Pod spawned: lab-alice-7d9f2 on fpga-01
✓ Board slot assigned: /dev/xilinx0
✓ JTAG proxy ready — routed in 1.8µs
$lf flash ./top_design.bit --verify
Flashing bitstream (24.3 MB)...
████████████████████ 100% 2.1s
✓ Verified. Board active.
$lf probe gpio --pin 24 --duration 200ms
PIN_24: ___‾‾‾___‾‾‾‾‾‾___‾ 1.002MHz Duty:62%
$lf test run ./suite/smoke.yaml
✓ 14/14 passed (3.2s)
CLK GPIO
<2µs
Session routing
64+
Board types
On-prem
Your infra, your network
Unlimited
Engineers / users
LabForge Design AI

Catch design flaws
before they reach
silicon.

LabForge Design AI is the AI design co-pilot embedded in your engineering workflow. It reviews electrical, mechanical, power, and system designs in real time — catching DRC violations, signal integrity issues, thermal problems, and COGS inefficiencies before you commit to fabrication.

labforge design ai — design review · power_board_v2.kicad_sch
Analysing power_board_v2.kicad_sch ...
✓ Electrical — 247 nets, 3 warnings
✗ U4 decoupling: 100nF missing on VDD_3V3
✗ R12 pull-up conflicts with I²C fast-mode spec
⚠ C22 rated 10V on 9.6V rail — derate to 25V
Analysing power tree ...
✓ Rail sequencing correct — 5V before 3.3V
✗ PDN impedance peak at 48MHz exceeds budget
Running COGS optimisation ...
✓ 3 alternate components found — save $0.42/unit
⚠ C14 (MLCC 10µF) — NRND, suggest TDK alt
2 errors · 3 warnings · est. BOM saving: $0.42/unit
4
Design disciplines
18%
Avg BOM cost reduction
Real-time
Review as you design
9+
EDA tool integrations
LabForge Showcase

Let prospects run code on your chip. Before they buy.

Embed a live hardware demo on your product page. A prospect clicks "Try on real silicon", gets a browser session on your actual board in under 60 seconds, and runs their own code. No dev kit. No account. No friction at the top of your sales funnel.

acmesemi.com/products/ax7-soc/try-live
AX7 — 32-bit RISC-V SoC
Live board · us-west-2 · 3 of 8 slots available
Live hardware
// Running your code on real AX7 silicon Board: AX7-EVK rev B (SN: AX7-00312) Core: RV32IMAC @ 200MHz Cache: 64KB → Uploading blinky.c ... flashed (0.8s) → UART output: Hello from AX7! tick=0 Hello from AX7! tick=1 Hello from AX7! tick=2
<60s
Time to first run
White-label
Your brand, your domain
No account
Zero friction to start
Any board
Custom silicon welcome
Boards supported Xilinx / AMD Intel / Altera STMicro NXP RISC-V SoCs Raspberry Pi CM Custom PCBs + 57 more
One platform, three layers

How LabForge Design AI, Studio
and Showcase connect.

Each layer does a distinct job. Together they close the loop from design intent through physical validation to customer demonstration — on the same hardware, with full traceability.

LabForge Design AI
Design & Verify
Pre-silicon · AI-assisted
Electrical schematic & PCB review
Mechanical, thermal & structural analysis
Power tree & EMI pre-compliance
System architecture & protocol compliance
COGS optimisation before sign-off
Generates test plans & acceptance criteria
test plans + criteria
LabForge Studio
Validate
Physical hardware · On-premises
Executes AI-generated test plans on real boards
JTAG, UART, GPIO, logic analyser — in the browser
CI/CD integration — runs on every PR
Session snapshots for collaborative debug
Fault signals fed back to LabForge Design AI for root-cause
64+ board types — or your own custom PCBs
validated silicon
Showcase
Demonstrate
Customer-facing · Managed SaaS
Live board sessions for prospects — in their browser
White-labeled under your brand and domain
Guided demo flows built from validated use cases
AI-vetted silicon = confident, reliable demos
Lead intelligence — who ran what, for how long
Replaces early-stage dev kit shipping
Design AI → LabForge Studio
AI designs the test. Lab runs it.
LabForge Design AI reads your design specs — timing budgets, thermal limits, current thresholds — and generates acceptance criteria. LabForge Studio executes these automatically on the physical board. When a fault is found, LabForge Design AI cross-references the signal capture against the original schematic to identify the root cause. No manual translation between design review and hardware test.
LabForge Studio → Design AI
Physical faults close the design loop.
When LabForge Studio finds unexpected behaviour on the board — a noisy rail, a timing violation, an unexpected current draw — it sends the captured signal data back to LabForge Design AI. The AI compares the fault against the original design review findings and tells you whether this was a flagged risk that slipped through or a new issue, and which schematic node to look at first.
LabForge Studio → Showcase
Validated silicon makes better demos.
The same boards used for internal validation become the Showcase pool for customer demos. Because LabForge Design AI has already vetted the design and LabForge Studio has run the test suite, you know exactly what the silicon can do reliably. Demo flows are built from validated use cases — not guesswork — so a prospect session on a Showcase board reflects the chip at its best, not at its edge cases.
LabForge Design AI

From first schematic
to optimized BOM —
AI at every step.

LabForge Design AI is the design co-pilot built into your lab. It reviews your electrical, mechanical, power, and system designs in real time, flags issues before they reach silicon, and optimizes your COGS before the design is locked. One platform from design intent to validated hardware.

Explore Design AI
01
Design & verify
AI reviews schematics, PCB layouts, power trees, and mechanical fits as you work — catching DRC violations, signal integrity issues, and thermal problems before you commit to fab.
02
Optimize COGS
Before sign-off, AI scans your BOM for cost reduction, second sources, lifecycle risk, and cross-product rationalization. Lock in the lowest manufacturable cost early.
03
Validate on real hardware
LabForge Studio runs the physical validation against AI-generated test plans and acceptance criteria derived from your design specs — closing the loop between intent and silicon behavior.
Electrical design
Schematic & PCB AI Review
AI co-pilot that works alongside your EDA tool — KiCad, Altium, Cadence, Eagle — reviewing your schematic and layout in real time. Catches issues that DRC rules miss.
Automated ERC / DRC with natural-language explanations — no cryptic error codes
Signal integrity analysis: impedance matching, crosstalk, return path violations
Net-level connectivity audit against design intent and interface specifications
Component placement review for manufacturability, rework access, and thermal spread
Decoupling strategy review: missing caps, wrong values, poor placement relative to switching nodes
Mechanical design
Enclosure, Thermal & Structural Analysis
AI review of PCB-to-enclosure fit, thermal path analysis, and structural integrity — catching mechanical issues before they become costly respins or field failures.
PCB outline vs enclosure fit check — connector clearances, mounting hole alignment, keep-out violations
Thermal hot-spot prediction from component placement and power dissipation maps
Stackup and layer count optimization for rigidity, signal isolation, and manufacturability
Vibration and shock risk scoring based on component mass, board dimensions, and mounting
IP rating pre-compliance checks — sealing, connector exposure, vent placement
Power design
Power Tree Analysis & EMI Pre-compliance
Full power architecture review from rail definition to EMC risk. AI models your power tree, identifies derating violations, estimates battery life, and flags pre-compliance risks before your board enters an EMC chamber.
Power tree completeness check — all rails accounted for, sequencing correct, no floating nodes
Component derating analysis at rated and worst-case temperatures
Battery / power budget estimation with load profile modeling across operating modes
EMI/EMC pre-compliance screening: clock harmonics, switching node loop areas, filtering adequacy
PDN (Power Delivery Network) impedance analysis and decoupling optimization
System design
Architecture Review & Interface Compliance
AI reviews your system architecture from block diagram to BOM — checking interface compatibility, standard compliance, and identifying architectural risks before a line of firmware is written.
Block diagram to BOM translation — verify every interface has a physical implementation
Protocol compliance checking: USB, PCIe, Ethernet, I²C, SPI, CAN — speed grades, loading, termination
Cross-system dependency mapping — clock domains, reset hierarchies, interrupt routing
Standards compliance pre-check: CE, FCC, UL, IEC — identify likely failures before formal testing
Firmware-hardware alignment: pin assignment review, peripheral configuration conflicts, IRQ collisions
COGS Optimization

Lock in your
lowest manufacturable cost
before you tape out.

COGS decisions made at the design stage are 10× cheaper to fix than post-prototype. LabForge Design AI analyses your BOM in context of your supply chain, assembly partner constraints, and product family — recommending changes that reduce cost without introducing risk.

Average BOM cost reduction seen by customers using LabForge Design AI COGS optimization before first prototype sign-off.

See COGS Analysis Demo
Avg BOM cost reduction
18%
Before first prototype sign-off
Single-source components eliminated
74%
Second sources identified automatically
Component lifecycle flags caught
NRND
Not Recommended for New Designs — flagged before commit
Cross-product rationalization
BOM
Consolidate parts across product families for volume pricing
What the AI reviews
Component alternates — same footprint, lower cost, available stock
Assembly yield optimization — placement density, pad geometry, wave soldering risk
Supply chain concentration risk — single distributor, long lead time, country-of-origin flags
Over-specification audit — components spec'd at 2× margin where 1.2× is sufficient
Works with your EDA tools KiCad Altium Designer Cadence Allegro Mentor PADS Eagle / Fusion 360 OrCAD LTspice ngspice MATLAB / Simulink
LabForge Studio

The engineering workbench.
For distributed hardware teams.

No lab booking queues. No "works on my bench". Give every engineer a dedicated board environment, fully reproducible — and plug it into your CI/CD pipeline on day one.

01
Deploy on your infrastructure
Install the LabForge Kubernetes stack on your own servers. Connect boards via USB, PCIe, or JTAG. Your IP and design files never leave your network.
02
Connect instantly
Sessions route at the lowest layer of the network stack. Sub-2µs latency makes JTAG timing indistinguishable from a local USB cable.
03
Flash, probe, debug
Upload bitstreams via CLI or Web IDE. Full JTAG breakpoints, UART console, GPIO capture, and 50Msps logic analyser — all in the browser.
04
Automate everything
GitHub Actions and GitLab CI integrations run hardware test jobs on real boards in your pipeline, just like any other build step.
JTAG over WebSocket
Full OpenOCD integration. Set breakpoints, inspect registers, read memory — from your browser or VS Code debug adapter. Works with GDB remotely.
OpenOCDGDB remoteVS Code
Logic analyser streaming
Capture GPIO, SPI, I²C, UART traces at 50Msps in real time. Browser-rendered waveforms with protocol decode. Export as VCD or CSV.
50MspsProtocol decodeVCD export
Sub-microsecond routing
Sessions route before conventional proxies wake up. No jitter, no dropped frames, fully deterministic timing — critical for hardware debug.
<2µs p99Zero jitterDeterministic
Emulation tier
QEMU and Renode cover 40+ MCU/SoC targets. Same CLI, same API as physical boards. Start CI pipelines before your hardware even arrives.
QEMURenode40+ targets
Session snapshots
Checkpoint a live board state mid-debug. Share the URL — a teammate restores the exact board state and continues the investigation from anywhere.
State captureShare URLRestore
CI/CD native
First-class GitHub Actions and GitLab CI integration. Hardware test jobs run on real boards in your pipeline just like any other step.
GitHub ActionsGitLab CIREST API

The JTAG latency is indistinguishable from a local cable. Our distributed team now debugs as if we're all sitting at the same bench.

RA
Riya Acharya
Senior FPGA Engineer, Inference Systems

200 board-level regression tests on every PR. Before Studio that meant someone physically flashing boards. Now it's a GitHub Action and takes 4 minutes.

MK
Marcus Kowalski
HW Platform Lead, Robotics Co.

Session snapshots saved us a full day. We caught a race condition at the exact moment of the glitch and shared it with engineers three timezones away.

SL
Sophie Laurent
Embedded Systems Architect, AutoTech
Studio Lab pricing

On-premises software. Annual license.

Studio Lab is priced by board slots you register — not by seat or lab-hour. Studio AI is a separate product with its own pricing.

Team
$12K
/ year — up to 16 board slots
  • Up to 16 registered board slots
  • Unlimited engineers / users
  • QEMU + Renode emulation included
  • CLI + Web IDE
  • CI/CD integration
  • Email support, 2-day SLA
  • Session snapshots + sharing
  • SSO / SAML
Request Trial License
Enterprise
Custom
/ year — unlimited board slots
  • Unlimited board slots
  • Air-gapped / classified deploy
  • Custom hardware integrations
  • Dedicated onboarding engineer
  • 24/7 support + named CSM
  • Source code escrow available
  • Custom SLA and DPA
  • Volume discounts
Talk to Sales
Free trial All tiers include a 30-day full-featured trial license. Install on your own cluster, connect your boards, and validate the platform before committing. Download Trial
Studio Lab Studio AI Showcase
LabForge Showcase

Turn your silicon into a live demo.

Embed Showcase on your product page. Prospects click "Try on real hardware", get a session on actual silicon in under 60 seconds, and run their own code. No dev kit, no account, no friction.

01
Connect your boards
Ship custom boards to a LabForge facility or deploy on-prem. We rack them, manage connectivity, and make them available as a shared pool for your prospects.
02
Embed the widget
One script tag on your product page. The live demo loads under your brand — your logo, colors, domain. Prospects never see LabForge.
03
Prospect clicks Try Live
No account required. A real silicon session spins up in under 60 seconds. Prospect uploads code and gets live UART output on your actual chip.
04
You close faster
Track which companies ran code, what they tested, how long they stayed. Trigger CRM workflows. Convert warm leads into dev kit orders weeks sooner.
Real silicon, not a simulator
Prospects run code on your actual chip. Real peripheral behavior, real timing, real UART output. The kind of experience that converts evaluators into buyers.
Physical boardsCustom PCBsAny silicon
Fully white-labeled
Your logo, your brand, your domain. Embed Showcase on your product page or host it at try.yourcompany.com. Prospects never see LabForge anywhere.
Custom domainYour brandingSSO optional
Zero friction to start
No account creation required. Prospect lands, clicks try, runs code in under 60 seconds. Optionally gate with email capture or OAuth for lead data.
No signupOAuth gate<60s to run
Guided demo flows
Build step-by-step guided experiences on the live session. Pre-loaded code examples, interactive prompts — walk prospects through your platform's strengths.
Step-by-stepPre-loaded codeCustom flows
Lead intelligence
See which companies ran code on your board, what they tested, for how long. Trigger Salesforce or HubSpot workflows when engagement crosses a threshold.
Session analyticsCRM webhooksSalesforce
Managed board pools
LabForge handles availability, resets between sessions, hardware failures, and scaling when demand spikes. You focus on silicon; we keep the boards running.
Auto-resetHA poolsManaged ops

We put "Try on real silicon" on our product page. Time-to-first-evaluation dropped from 3 weeks to under 2 minutes. Pipeline conversion jumped 40%.

JN
James Nakamura
VP Sales, RISC-V Semiconductor Co.

Our DevRel team used to spend 80% of their time shipping eval kits. Showcase eliminated that entirely. We focus on the developers who are actually serious.

AP
Ananya Patel
Head of Developer Relations, SoC Startup

The lead intelligence is genuinely useful. A company spent 45 minutes running motor control code on our chip — we called them the same day. Closed in two weeks.

TR
Tom Reeves
Director of Field Applications, Power IC Co.
Showcase pricing

Priced per board slot. Not per prospect.

You pay for hardware slots you expose to your customers. Your prospects pay nothing — that's the whole point.

Starter
$299
/ month
  • Up to 4 concurrent board slots
  • 1 board type
  • Standard LabForge branding
  • Basic session analytics
  • Custom domain / white-label
  • CRM webhooks
Get Started
Enterprise
Custom
/ dedicated pool
  • Unlimited board slots
  • Unlimited board types
  • On-prem deployment
  • Custom integrations
  • Dedicated support + SLA
  • Co-marketing opportunities
Talk to Sales

How do boards connect to LabForge?

Studio + Showcase
LabForge-hosted hardware
LabForge owns physical boards in its own data centers. Pick from the catalog, reserve a slot, get access. No shipping, no setup, no maintenance on your end.
How it works
  • LabForge racks standard boards across US, EU, and APAC
  • You pick a board type when creating a session or Showcase pool
  • LabForge handles power cycling, firmware recovery, and failures
  • Best for: standard eval boards, university labs, early CI/CD
Showcase + Studio Enterprise
Co-located custom boards
Ship your proprietary PCBs to a LabForge facility. We rack them using a standard carrier tray and manage all connectivity. You own the boards; we own the ops.
How it works
  • LabForge ships a carrier tray spec for your board's form factor
  • You ship boards — our techs install and register hardware IDs
  • JTAG, UART, power, and GPIO headers exposed to the cluster
  • Best for: custom silicon, proprietary PCBs, Showcase deployments
Studio + Showcase Enterprise
On-premises self-hosted
Install LabForge's platform in your own facility. Connect boards to your own servers. Everything runs inside your network — no traffic leaves the building.
How it works
  • Deploy the LabForge Kubernetes stack on your own infrastructure
  • Connect boards via USB, PCIe, or JTAG adapters to worker nodes
  • LabForge node agent registers attached hardware with the cluster
  • Best for: defense, semiconductor IP, air-gap, classified designs
Frequently asked questions

Everything buyers ask
before they commit.

Answers for all three products. Switch below.

Deployment & infrastructure
Entirely on your own infrastructure. Studio is a Kubernetes-based platform you install and operate inside your own network. No data, no design files, and no board signals ever leave your premises. You bring the servers; LabForge provides the software that turns them into a managed hardware lab platform.
You deploy a Helm chart into an existing Kubernetes cluster. LabForge runs as a set of pods — the lab orchestrator, session controller, and a DaemonSet node agent on each worker node that has boards attached. No external dependencies at runtime; the license is verified on initial activation and renewed annually. Your IT team manages it like any other internal Kubernetes workload.
Yes. The Enterprise tier is specifically designed for air-gapped networks. Container images are provided as a portable bundle for import into your internal registry. License verification can be done offline via a hardware token or one-time activation code. We have customers running Studio in ITAR-controlled and classified environments with zero internet connectivity.
Minimum: Kubernetes 1.26+, at least one worker node per board type, Linux kernel 5.15+ on worker nodes. Control plane needs 4 vCPU, 8 GB RAM, 50 GB storage. Worker nodes hosting physical boards need USB or PCIe passthrough configured. We provide a pre-install checklist and runbook for common cluster configurations — bare metal, VMware, EKS, and GKE.
Hardware & boards
Boards connect to worker nodes via USB, PCIe, or a JTAG adapter — the same physical connection you'd use at a bench. The LabForge node agent detects attached hardware and registers it with the cluster using a device plugin that exposes boards as Kubernetes resources (e.g. hardware.lab/fpga-xilinx=4). The scheduler then places lab pods on the correct node with direct access to the right board.
Yes — this is one of the primary reasons customers choose Studio over vendor-specific tools. Any board that exposes a standard debug interface (JTAG, SWD, UART, or GPIO) can be registered. You provide a board definition YAML with pin mappings and interface configuration, and Studio handles the rest. Our professional services team can help create board definitions for complex custom silicon during onboarding.
Studio includes a hardware health monitoring agent that detects unresponsive boards and triggers automated recovery — power cycling via a managed PDU, re-flashing to known-good baseline firmware, then marking the board available again. For failures requiring physical intervention, Studio drains the board slot, surfaces an alert in the admin dashboard, and sends a webhook or email to on-call. When a technician brings the board back online, Studio automatically re-registers it.
By default, board slots are exclusively reserved per session — just like a physical bench. Only one lab pod holds a given board at a time. However, Studio supports a collaboration mode where multiple engineers can join the same session as observers or co-operators, sharing the terminal, signal traces, and GPIO state. This is separate from concurrent exclusive access, which is governed by the board slot scheduler.
Security & IP protection
No. Because Studio is entirely on-premises, LabForge has zero visibility into your designs, bitstreams, firmware, or board behavior. The only outbound connection is the license renewal check — and even that is replaced by an offline token in the Enterprise tier. Your IP stays inside your network, full stop.
Studio uses role-based access control. Boards are grouped into pools (e.g. "FPGA Lab", "MCU Validation Bench") and pools are assigned to teams or users via policy. An engineer on the firmware team can only access boards in their designated pool. Admins can enforce time-limited reservations, require approval for certain board types, and audit every session — who accessed which board, when, for how long, and what files were uploaded.
Yes. The Engineering and Enterprise tiers include SAML 2.0, OIDC, and LDAP integration. Studio authenticates against Okta, Azure AD, Google Workspace, Ping Identity, or any standards-compliant IdP. Group membership from your IdP maps directly to board pool permissions, so you manage access in one place and it propagates automatically.
Licensing & commercial
One board slot is one registered hardware endpoint — one physical board (or one emulated virtual board) that Studio manages. If you have 8 FPGA boards and 8 MCU dev kits, that's 16 board slots. The number of engineers who can access those boards is unlimited at all tiers. You're paying for the breadth of your hardware lab, not the size of your team.
The trial is the full Engineering tier — no feature restrictions. You install Studio on your own cluster, register your own boards, and use every capability including SSO, session snapshots, and CI/CD integration. No credit card required, no automatic conversion to paid. At the end of 30 days you either purchase a license or the software stops accepting new sessions. Existing configurations are preserved if you license within 14 days of expiry.
Support is included at all tiers — email support at Team level (2-business-day response), priority support at Engineering level (8-hour response), and 24/7 named support at Enterprise. Software updates and minor releases are included throughout the year. Major version upgrades are included for the first year and discounted in subsequent years. Professional services are available separately.
What Studio AI does
Studio AI runs continuously as you design — not as a batch job you trigger at the end. It integrates with your EDA tool and analyses your schematic, PCB layout, power tree, and system architecture in real time. You see findings as you place components and route traces, not after you've submitted for fabrication. The four disciplines — Electrical, Mechanical, Power, and System — are each analysed by a separate AI model trained on design rules, datasheet data, and manufacturing constraints.
EDA tool DRC catches geometric and connectivity violations defined by explicit rules — clearance, trace width, missing connections. Studio AI catches issues that require contextual understanding: a capacitor that passes DRC but is placed too far from its load to be effective, a power rail that sequences correctly but starves a peripheral during startup, an interface that meets voltage spec but violates the protocol timing budget at operating temperature. These are the issues that survive DRC and show up as board failures.
Both. You can import an existing schematic or PCB file for a one-time design audit — useful for inherited designs, designs from acquisitions, or boards going through a second spin. For new designs, Studio AI runs continuously as a background co-pilot. The audit mode produces a prioritised finding report with severity ratings, affected nets or components, and recommended fixes. Most teams run an audit on every existing product before the next revision.
Yes. Studio AI maintains a continuously updated component knowledge base covering millions of parts — operating ranges, derating curves, recommended application circuits, known errata, lifecycle status, and second-source equivalents. When it flags a component issue, it references the specific datasheet parameter it's checking against. You can also upload proprietary component data sheets for custom or ASIC parts that aren't in the public database.
COGS & supply chain
After you upload your BOM, Studio AI cross-references every line item against live distributor pricing, availability data, lifecycle status, and your existing approved vendor list. It then generates an alternate BOM with suggested substitutions — same footprint, same function, lower cost or better availability — ranked by estimated BOM cost saving and risk level. Each suggestion includes the alternate part number, a datasheet comparison, and whether any schematic changes are needed. You approve or reject each suggestion; Studio AI learns your preferences over time.
Single-source components are flagged automatically with a risk score based on manufacturer concentration, lead time history, and geopolitical supply chain factors. For each flagged part, Studio AI identifies qualified second sources — parts that are electrically equivalent and pin-compatible, sourced from a different manufacturer or country of origin. Where a direct drop-in doesn't exist, it flags the design change required to qualify an alternate. This runs at BOM import time and again whenever distributor availability or lifecycle data changes.
Yes — cross-product BOM rationalisation is one of the highest-value features. Upload BOMs from multiple products and Studio AI maps component overlap across your portfolio, identifying opportunities to standardise on a single part number where two products currently use non-identical but functionally equivalent parts. Consolidating to common components unlocks volume pricing breaks, simplifies procurement, and reduces your approved vendor list complexity. This analysis runs across your full portfolio and updates whenever a new BOM is added.
Integration & workflow
Studio AI integrates with KiCad (open API, deepest integration), Altium Designer and Altium 365, Cadence Allegro and OrCAD, Mentor PADS and Xpedition, Eagle / Autodesk Fusion 360, LTspice and ngspice for simulation file ingestion, and MATLAB/Simulink for system model import. The integration depth varies by tool — KiCad and Altium support live continuous review; other tools support file-based import for batch analysis. The Essentials tier includes KiCad and Altium; all nine integrations are available at Professional and above.
When Studio AI completes a design review, it generates a test plan — a set of acceptance criteria derived from your design specs: expected rail voltages, timing budgets, thermal limits, current thresholds, interface signal levels. Studio Lab ingests this test plan and runs it automatically on the physical board. When the board is flashed and powered, Studio Lab checks each criterion and reports pass/fail against the AI-generated baseline. If a criterion fails, the signal capture is sent back to Studio AI which cross-references it against the original schematic finding to identify root cause. This closes the loop between design intent and physical behavior without manual translation.
The Professional tier runs AI inference in LabForge's cloud — your design files are sent over an encrypted connection, processed, and findings returned. Design data is never stored after the session ends and is never used for model training. The Enterprise tier supports on-premises AI inference for organisations that cannot send design files off-site — the AI models run on your own GPU servers. This is the mode used by customers with export-controlled designs, ITAR requirements, or classified IP.
Accuracy & trust
Studio AI is designed to be a co-pilot, not an oracle. Every finding includes a confidence score, a specific reference (the datasheet parameter, the design rule, the protocol spec) it's checking against, and a clear explanation of why it's flagged. Engineers treat it like a knowledgeable colleague flagging something to check — not an automated verdict. In practice, customers find that high-confidence findings (above 85%) are correct over 90% of the time. Low-confidence findings are surfaced as "worth a look" rather than errors. You can tune the sensitivity threshold per discipline.
Every finding has a one-click "dismiss with reason" action. When you dismiss a finding — either because it's a false positive or because you've made a conscious design decision — Studio AI learns your context. If you dismiss a finding with an explanation (e.g. "this capacitor placement is intentional for thermal reasons"), that note is stored and the same pattern won't be flagged again on this design. Dismissal data is used to improve the model for all customers on an anonymised, opt-in basis.
Yes, in the Enterprise tier. You can upload a custom design rule library — your organisation's internal standards, your CM's process capabilities, your approved vendor list, your derating policies — and Studio AI applies these alongside its built-in rules. Custom rules take precedence over default rules when they conflict. This means Studio AI enforces your company's design standards automatically across every designer on your team, not just the ones who remember to check the style guide.
How Showcase works
A browser-based lab environment loads embedded in your product page — under your brand and domain. Within 60 seconds a session is live on a real board. They see a terminal with UART output, can upload their own code or use pre-loaded examples, flash it, and see real output immediately. No plugins, no downloads, no account required to start.
Real hardware, every time. Every Showcase session connects to a physical board — your actual chip. Simulators approximate behavior but they can't reproduce exact peripheral timing, power characteristics, and edge cases of real silicon. When a prospect's code runs on a Showcase board and it works, they have genuine confidence it will work on the hardware they're about to buy. A simulator cannot offer that.
One JavaScript snippet added to your page — similar to embedding a Calendly widget. The Showcase widget loads in an iframe, fully styled to match your brand. Alternatively, host a dedicated experience at a subdomain like try.yourcompany.com with a full-page layout. Both support custom CSS theming, your logo, and your product documentation alongside the live session. LabForge branding is completely absent.
Yes, at multiple levels. You can restrict sessions to a curated library of pre-loaded examples, allow free code upload within file type and size limits, or set an allowlist of permitted operations. Peripheral access can also be scoped — a prospect might have UART and GPIO access but not JTAG, depending on what you want to expose. The board is automatically wiped and restored to a clean baseline between sessions.
Boards & hardware logistics
Three options. Co-location: ship your boards to a LabForge facility and we rack and manage them using a standard carrier tray. On-prem: deploy Showcase infrastructure on your own premises with boards connected locally. Hybrid: LabForge-hosted boards for public demos, your own boards for sensitive workloads. Most hardware vendors choose co-location — no infrastructure investment beyond shipping populated boards.
Showcase has an automated session recovery system. At the end of every session (or on crash detection), the board goes through an automatic reset — power cycle, restore golden firmware image, health check — before being marked available again. This typically takes 30–60 seconds. If a board fails to recover after three attempts it's removed from the pool and an alert fires. A prospect who hits a failed session is automatically offered the next available slot.
Sessions typically run 10–30 minutes. With 8 board slots you can serve roughly 20–50 unique prospects per day before introducing wait times. We recommend 2–4× your expected peak concurrent load. Showcase has a built-in queue with estimated wait time so prospects don't hit a dead end during spikes — they join the queue and get notified when a slot opens. For co-located boards, we can add capacity within 3–5 business days of a request.
Security & prospect data
The exposure is comparable to shipping a physical dev kit — perhaps less, because you control which interfaces are accessible. Prospects can run code and observe behavior, but you can restrict JTAG access, prohibit memory dumps, and sandbox which peripherals are reachable. For sensitive pre-production silicon, many customers use Showcase only for publicly announced products — using it to accelerate developer adoption of launched chips rather than early evaluation vehicles.
For gated sessions (email or OAuth login required): full session analytics — company, email, session duration, code uploaded, peripherals accessed, and return visits. This can be pushed to Salesforce, HubSpot, or any CRM via webhook in real time. For ungated sessions: aggregate engagement data without individual identity. You own all prospect data — LabForge does not use it for any other purpose.
Completely. Every session gets an exclusive, isolated board and a dedicated pod with no shared filesystem or network path to any other session. A prospect cannot see another user's code, session state, or UART output. Between sessions the board is fully reset and the pod is destroyed — no state persists. Even if two prospects are on the same board model simultaneously, they are on separate physical boards with zero shared resources.
Commercial & integration
Yes. Showcase is designed to be embedded, not to replace your dev portal. The JavaScript widget drops into any page. For tighter integration, the Showcase API lets you programmatically create sessions, pre-load specific firmware, and pass authenticated user context from your portal's SSO — so a logged-in developer already knows who they are when the session starts.
For standard boards in the LabForge catalog: 1–2 weeks from contract to a live embed. For custom boards requiring co-location: 3–4 weeks, including shipping, tray installation, and board definition setup. The widget integration on your side is a single afternoon. Every new Showcase customer gets a dedicated onboarding engineer who handles board setup, demo flow design, and widget configuration.
For early-stage evaluation — yes, for most prospects. A developer who would have requested an eval kit to answer "will this chip do what I need?" can answer that in a 20-minute Showcase session without waiting weeks. You still need physical kits for customers moving into active design-in and production validation. Think of Showcase as the top of the funnel — it qualifies developers before they invest in a kit. The customers who request a kit after a Showcase session are considerably more serious.
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